IC test cell with memory output connected to input multiplexer

ABSTRACT

A test cell ( 12 ) provides boundary scan testing in an integrated circuit ( 10 ). The test cell ( 12 ) comprises two memories, a flip-flop ( 24 ) and a latch ( 26 ), for storing test data. A first multiplexer ( 22 ) selectively connects one of a plurality of inputs to the flip-flop ( 24 ). The input of the latch ( 26 ) is connected to output of the flip-flop ( 24 ). The output of the latch ( 26 ) is connected to one input of a multiplexer ( 28 ), the second input to the multiplexer ( 28 ) being a data input (DIN) signal. A control bus ( 17 ) is provided for controlling the multiplexers ( 22, 28 ), flip-flop ( 24 ) and latch ( 26 ). The test cell allows input data to be observed and output data to be controlled simultaneously.

RELATED APPLICATIONS

[0001] This Application is related to co-pending Application for U.S.patent Ser. No. ______, filed ______, entitled “TestingBuffer/Register”, incorporated herein by reference.

[0002] This Application is related to co-pending Application for U.S.patent Ser. No. ______, filed ______, entitled “Enhanced Test Circuit”,incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

[0003] This invention relates in general to integrated circuits, andmore particularly to a test cell used in an integrated circuit forproviding a boundary scan test structure.

BACKGROUND OF THE INVENTION

[0004] Due to advances in the fields of board interconnect technology,surface mount packaging and IC density, board level testability isbecoming increasingly complex. The combination of advanced boardinterconnect technology, such as buried wire interconnects anddouble-sided boards, along with surface mount packaging creates problemsfor in-circuit testing of the boards. In-circuit testing, the mostcommon board level testing method, depends upon the ability tophysically probe the nodes of a circuit board. As board density (thenumber of ICs on a board) increases, the process of probing the boardusing traditional techniques becomes more difficult, due to the lack ofphysical access.

[0005] As the IC density (amount of logic on a chip) increases, thenumber of test patterns required for proper testing likewise increases.In-circuit testing relies on back-driving techniques to force inputconditions to test a particular IC in a circuit. When such test is beingapplied to one IC on a board, neighboring ICs, whose output buffers aretied to the same nodes, may be damaged. The chance of damaging aneighboring IC increases with the length of time it takes to perform atest, which is directly related to the number of test patterns applied,and therefore, related to the IC density.

[0006] Therefore, a need has arisen in the industry to provide a teststructure which provides access to particular ICs on a board, and allowstesting of particular ICs without risk of damage to neighboring ICs.

SUMMARY OF INVENTION

[0007] In accordance with the present invention, a boundary scan testsystem is provided which substantially eliminates the disadvantages andproblems associated with prior testing systems.

[0008] The boundary scan test system of the present invention comprisesa first multiplexer connecting a plurality of induts to a first memory,responsive to control signals provided by a control bus. The output ofthe first memory is connected to a second memory. The output of thesecond memory is connected to an input to a second-multiplexer alongwith one or more other inputs. The second multiplexer is controlled byanother control signal on the control bus. The output of the firstmemory and the output of second memory are connected to the firstmultiplexer as inputs.

[0009] The present invention provides a variety of functions for testingpurposes. The test cell is operable to both reserve data inputs andcontrol data outputs to and from the cell. The test cell may operate intwo modes: “normal” mode and “testing” mode. In normal mode, the testcell provides a data path through which inputs and outputs may propagatefreely through the test cell. While in the normal mode, the test cellcan also load and shift test data, remain in an idle state, or toggletest data without disturbing the normal operation of the integratedcircuit. Further, while in normal mode, a predetermined test data bitmay be inserted into the data stream. Also, the test cell may perform aself-test while in the normal mode to insure correct operation of thetest cell.

[0010] In the test mode, the test cell inhibits the normal flow of datathrough the test cell. Normally, the test cells in the integratedcircuit will have been prepared to output an initial test pattern. Whilein the test mode, the test cell may perform Idle, Load, Shift, andToggle operations.

[0011] The present invention provides significant advantages over theprior art. First, the test cell of the present invention may be used toperform internal and external boundary testing simultaneously, in orderto reduce overall test time. Second, the test cells are capable ofsampling or inserting data at the boundary during normal operation ofthe host integrated circuit. Third, the test cell is synchronous inoperation with a free running test clock. Fourth, the present inventionprovides a method of toggling an IC's output buffers, independent of theIC's application logic, in order to achieve parametric measures and tofacilitate boundary test. Fifth, the test cell provides self-testingcapabilities.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present invention andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings, inwhich:

[0013]FIG. 1 illustrates circuit diagram of an integrated circuit havingtest cells disposed at the boundary of the internal application logic;

[0014]FIG. 2 illustrates a circuit diagram of a preferred embodiment ofthe test cell of the FIG. 1;

[0015]FIG. 3 illustrates a circuit diagram interconnections between testcells on an integrated circuit;

[0016]FIG. 4a illustrates a circuit diagram of a preferred embodiment ofa bidirectional test cell;

[0017]FIG. 4b illustrates a diagram of the bidirectional test cell ofFIG. 4a as disposed within an integrated circuit; and

[0018]FIG. 5 illustrates an implementation of the test cell of thepresent invention.

[0019]FIG. 6 illustrates a test circuit comprising a base test cell withcompare logic circuitry;

[0020]FIG. 7 illustrates a test circuit comprising a base test cell withPRPG/PSA logic circuitry;

[0021]FIG. 8 illustrates a test circuit comprising a base test cell withPRPG/PSA logic circuitry and programmable Polynomial tap logiccircuitry;

[0022]FIGS. 9a-b illustrate interconnections between test circuitshaving programmable polynomial tap logic circuitry;

[0023]FIG. 10 illustrates a bidirection test cell having PRPG/PSA testcircuitry;

[0024]FIG. 11 illustrates a bidirectional test cell having PRPG/PSA testcircuitry and programmable polynomial tap circuitry;

[0025]FIG. 12 illustrates a circuit using test devices to observe inputsand control outputs to and from standard combinational logic;

[0026]FIG. 13 illustrates a circuit diagram of a preferred embodiment ofa test device of FIG. 12;

[0027]FIG. 14 illustrates a circuit diagram of a test device performingPSA operations; and

[0028]FIG. 15 illustrates a circuit diagram of a test device performingsimultaneous PSA and PRPG operations.

DETAILED DESCRIPTION OF THE INVENTION

[0029] The preferred embodiment of the present invention is bestunderstood by referring to FIGS. 1-5 of the drawings, like numeralsbeing used for like and corresponding parts of the various drawings.

[0030]FIG. 1 illustrates a block diagram of an integrated circuit (IC)10 having test cells 12 a-h disposed about its boundary to control andobserve data flow through the application logic 14 of the IC 10. Theintegrated circuit 10 comprises a plurality of pins 16 which provide anelectrical connection between the integrated circuit 10 and otherintegrated circuits. For purposes of illustration, the integratedcircuit 10 is shown with four pins receiving input signals, IN1, IN2,IN3 and IN4, and four pins providing output signals, OUT1, OUT2, OUT3and OUT4 Other signals to the chip include a serial data input (SDI), acontrol bus 17, and a serial data output (SDO). The input signalsIN1-IN4 are connected to input buffers 18 which output to respectivetest cells 12 a-d. Each test cell 12 a-h has its own serial data inputand serial data output, enumerated SDI 1-8 and SDO 1-8. In theillustrated configuration, the SDI input to the IC 10 is connected toSDI1 of test cell 12 a; the SDI induts of subsequent cells 12 b-hreceive the SDO of the previous cell. Hence, SDO1 is connected to SDI2,SDO2 is connected to SDI3, and so on. SDO8 is connected to the SDO pinof the IC 10. The control bus 17 is connected in parallel to each of thetest cells 12 a-f.

[0031] Each test cell includes a data input (DIN) and a data output(DOUT). For the input test cells 12 a-d, DIN is connected to the outputof respective buffers 18 and DOUT is connected to the inputs of theapplication logic 14. The inputs of the application logic 14 areenumerated IN1′-IN4′, corresponding to the inputs IN1-IN4. IN1′-IN4′would be the inputs to the chip were not the test structure provided.

[0032] The output from the application logic 14 are referenced as OUT1′,OUT2′, OUT3′ and OUT4′. The outputs of the application logic OUT1′-OUT4′are connected to the data inputs (DINs) of the output test cells 12 e-h.The data outputs (DOUTs) of the output test cells 12 e-h are connectedto output buffers 20 corresponding to OUT signals OUT1-OUT4.

[0033] The test cells 12 a-h provide the basis for a great deal of testfunctionality within the integrated circuit 10. The SDI enters the IC 10through test cell 12 a and may propagate to each subsequent cell 12 b-h,eventually being output from test cell 12 h through SDO8. The serialdata path is used to shift data into and out of each of the test cells12 a-h.

[0034] The control bus provides signals for operating each of the testcells 12 a-h during testing, and is described in more detail inconnection with FIGS. 2-3. When placed in a test mode, the test cells 12a-h inhibit the normal flow of data into and out of the IC 10. In thetest mode, each test cell 12 a-h controls the logic node attached to itsoutput and observes the logic node attached to its input. For example,in FIG. 1, the test cells 12 a-d attached to the four inputs IN1-IN4,can observe the logic levels on the IN1-IN4 inputs and control the logiclevels on the IN1′-IN4′ outputs. Similarly, the test cells 12 e-h,connected to the four outputs can observe the logic levels on theOUT1′-OUT4′ inputs and control the logic levels on the OUT1-OUT4outputs.

[0035] In FIG. 2, a detailed block diagram of an individual test cell 12is provided. The test cell 12 has three data inputs: data in (DIN),observability data in (ODI), and serial data in (SDI). Two data outputsare provided: data out (DOUT) and serial data out (SDO). The control bus17 comprises five signals, data input multiplexer selects, A and B, aregister clock signal (CLK), a latch enable (HOLD), and a data outputmultiplexer select (DMX).

[0036] A first multiplexer 22 receives the ODI and SDI signals, alongwith the output of a D-type flip-flop 24 and the inverted output of aD-type latch 26. The output of the multiplexer 22 is connected to theinput of the flip-flop 24. The CLK signal is connected to the flip-flopclock input. The output of the flip-flop 24 is connected to the input ofthe latch 26 and also provides the SDO signal. The output of the latch26 is connected to the input of a second multiplexer 28 along with theDIN signal. The HOLD signal is connected to the latch enable. The outputof the multiplexer 28 provides the DOUT signal. The multiplexer 28 isenabled by the DMX signal.

[0037] In operation, the 4:1 multiplexer 22 allows the input to theflip-flop 24 to be selected from one of four possible sources: ODI, SDI,the output of the flip-flop 24 or the inverted output of the latch 26.The latch 26 can be controlled to propagate the output of the flip-flop24 or to hold its present state, depending upon the logic level appliedby the HOLD input. The 2:1 multiplexer 28 allows the DOUT output to bedriven by either the DIN input or the output of the latch 26, dependingupon the logic level applied by the DMX input. The combination of the4:1 multiplexer 22, flip-flop 24, latch 26 and 2:1multiplexer allows thetest cell 12 to operate in four synchronous modes: load, shift, toggleand idle.

[0038] In load mode, the test cell 12 clocks the logic state of the ODIinput into the D flip-flop 24 through the multiplexer 22. The ODI inputis coupled to a signal that is to be observed during tests and, in mostcases, the ODI input will be attached to the same boundary signal thatis connected to the test cell's DIN input. However, the ODI can beconnected to other signals as well. To cause a load operation to occur,the A and B inputs are set to predetermined levels, allowing the ODIinput to be connected to the flip-flop 24 via the 4:1 multiplexer 22.Normally, the HOLD input to the latch 26 is low, forcing the latchoutput to remain in its present state during a load operation.

[0039] In shift mode, the test cell clocks the logic state of the SDIinput into the flip-flop 24 and outputs this logic state via the SDOoutput. The shift mode allows the test cells 12 in the boundary scanpath to be interconnected together so that serial data can be shiftedinto and out of the boundary scan path. In a boundary scanconfiguration, the SDI input of the test cell is coupled to a precedingtest cell's SDO output, as shown in FIG. 1. To cause the shift operationto occur, the A and B inputs are set to predetermined levels, allowingthe SDI input to be connected to the flip-flop 24 via the 4:1multiplexer. Normally, the HOLD input to the latch 26 is kept low,forcing the latch output to remain in its present state during the shiftoperation.

[0040] In toggle mode, the output of the flip-flop 24 toggles betweentwo logic states at the rate of the CLK input, regardless of thecondition of the SDI or ODI inputs. In this configuration, the HOLDinput is set to a high logic level to enable the latch 26 and the A andB inputs are set such that the inverted output of the latch 26 ispropagated to the flip-flop 24. With the control input set in thismanner, a feedback path is formed from the output of the flip-flop 24 tothe input of the latch 26 and from the inverted output of latch 26 tothe input of the flip-flop 24. Because of the data inversion at theinverted output of the latch 26, the opposite logic state is clockedinto the flip-flop 24 on each CLK input, creating the toggle effect.

[0041] In idle mode, the test cell remains in present state while theCLK is active, regardless of the condition of the SDI or ODI inputs. Inthis configuration, the output of the flip-flop 24 is passed through the4:1 multiplexer 22; hence, the input of the flip-flop 24 is connected toits output, allowing the present state of the flip-flop 24 to berefreshed on every clock input.

[0042] The test cell 12 can be in either “normal” mode or “testing”mode. In normal mode, the test cell 12 provides the data path throughwhich the inputs (IN1-IN4) and output (OUT1-OUT4) propagate freely. Thenormal mode is achieved by setting the DMX signal such that the DINsignal passes through the multiplexer 28 to DOUT. While in the normalmode, the test cell 12 can operate in any of the four synchronous modes(load, shift, idle or toggle) without disturbing the normal operation ofthe IC 10.

[0043] A control signal can be issued via the A and B inputs to causethe test cell 12 to execute a load operation. The load operation causesthe test cell 12 to capture the logic level present on the ODI input.Once the data has been captured, it can be shifted out of the test cell12 by performing a shift operation. The load operation occurssynchronous with the CLK input. Following the shift operation, the testcell 12 typically returns to the idle mode. This capability allows thetest cell 12 to sample an IC's input and/or output boundary signals andshift the sample data out for inspection during normal operation of theIC. The ability to sample boundary data during normal operations allowsthe test cell 12 to verify the functional interactions of multiple ICson a circuit board without having to use expensive test equipment andexternal test probes.

[0044] Also while in normal mode, control can be issued via the DMXinput to cause the test cell 12 to insert a predetermined test data bitinto the normal input/output boundary path of the IC. The test data bitto be inserted is shifted into the flip-flop 24 via a shift operation.The HOLD input to the latch 26 is set high to allow the test data in theflip-flop to pass through the latch and input to the 2:1 multiplexer 28.To insert the test data, the DMX input is set to a level causing themultiplexer to propagate the test data from the output of the latch 26to the DOUT output. After the test data has been inserted, the DMX inputis switched to cause the 2:1 multiplexer 28 to propagate normal datafrom DIN to DOUT.

[0045] The ability to insert test data during normal operations allowsthe test cells to modify the normal behavior of one or more ICs in acircuit. One particular usage of the insert capability is to propagate afault into the input and/or output boundary of one or more ICs of acircuit board to see if the fault can be detected and corrected. Inorder to perform the sample and insert test functions during normaloperation, the test cell 12 must receive control via the control bus 17at a qualified point in time.

[0046] The test cell 12 can also perform a self-test while in the normalmode without disturbing the normal operation of the IC 10. A shiftoperation may be performed to initialize the flip-flop 24 to a knownstate. Following the shift operation, control is issued to cause thetest cell 12 to enter the toggle mode for one CLK transition. Duringthis transition, the flip-flop is loaded with the inverse of its state.Following this inversion of data, another shift operation is performedto retrieve the contents of the flip-flop 24 and verify the inversionoperation. This test verifies the combined operation of each of the testcell's flip-flop 24, 4:1 multiplexer 22, and latch 26, along with theintegrity of the overall boundary scan path.

[0047] In the test mode, the test cell 12 inhibits the normal flow ofdata from the DIN input to the DOUT output. The test mode is entered bysetting the DMX input to a level such that the output of the latch 26 isconnected to the DOUT output. Normally, prior to entering the test mode,the test cell 12 will have been prepared to output an initial testpattern, via a shift pattern. Also, the test cell 12 will usually be inan idle state and the HOLD input to the D latch will be set low, suchthat its present output is maintained.

[0048] While in the test mode, a load operation may be executed, causingthe test cell 12 to capture the logic level present on the ODI input.The load operation occurs synchronous with the CLK input. During a loadoperation, the HOLD input is set low, such that the D latch remains inits present state. Likewise, the DOUT output remains in its presentstate, since it is driven by the latch output.

[0049] Following the load operation, a shift operation is performed,causing the test cell 12 to shift data through the flip-flop 24 from theSDI input to the SDO output. The shift operation allows the test cell toshift out the data captured during a previous load operation and shiftin the next output test data to apply to the DOUT output. The shiftoperation occurs synchronous with the CLK input. During a shiftoperation, the HOLD input is held low, such that the output of the latch26 remains in its present state. Likewise, the DOUT output remains inits present state, since it is driven by the latch output.

[0050] Following the load and shift operation sequence, the test cell 12returns to the idle mode and the HOLD input will be set high, such thatthe latch 26 is updated with the new output test data residing in theflip-flop 24. When the latch 26 is updated, the new output test data isapplied to the DOUT output. Following the update operation, the HOLDinput is set low such that the latch 26 remains in its present stateduring subsequent load and shift operations.

[0051] The HOLD, load, shift, and update/apply sequence is repeatedduring boundary scan testing of the internal and external logic elementsattached to the ICs test circuitry. By providing separate memoryelements for output test control (i.e., latch 26) and input testobservation and shifting (i.e., flip-flop 24), the test cell 12 can testthe internal logic of an IC 10 and the external logic and/or wiringinterconnects attached to the IC's boundary simultaneously. This featurereduces test time significantly.

[0052] While in the test mode, the test cell 12 can perform a toggleoperation. Since the output of the latch 26 is coupled to the DOUToutput during test mode, the DOUT output can be made to toggle at therate of the CLK input when the toggle operation is performed. Theadvantage of using a D latch instead of a second D flip-flop is that theD latch can be made to propagate the Õ output of the D flip-flop bysetting the HOLD input high. The toggle mode can be used as a simpletest pattern generator or for measuring parameters of the output buffers20 of the IC 10.

[0053]FIG. 3 illustrates a simplified view of an IC design having oneinput (IN), one output (OUT), an application logic section 4, and aboundary scan path consisting so two test cells 12 i and 12 j. The inputto the application logic 14 is connected to the output of the 2:1multiplexer 28 of test cell 12 i, and is denoted as IN′. The output ofthe application logic is denoted as OUT′ and is connected to the DIN andODI signals of the test cell 12 j.

[0054] The IN input enters the DIN input of the input test cell 12 i,passes through the 2:1 multiplexer 28, and is output to the applicationlogic 14 from the input test cells DOUT output, via IN′. Likewise, theapplication logic output, OUT′, enters the DIN input of the output testcell 12 j, passes through its 2:1 multiplexer 28, and is output from theIC from the output test cell DOUT output, via OUT. The ODI input of theinput test cell 12 i is attached to the ICs input (IN) and the ODI inputof the output test cell 12 j is attached to the application logic output(OUT′). The SDI input of the IC is coupled to the input test cell's SDIinput and the IC serial data output (SDO) is coupled to the output testcell SDO output. A serial data path exists between the SDO of the inputtest cell 12 i output and the SDI input of the output test cell 12 j,creating an internal connection between the test cells for shiftingdata. The control bus signals (A, B, CLK, HOLD, and DMX) are connectedto both test cells 12 i and 12 j, allowing both to operate together in asynchronous manner.

[0055] In the normal mode, data flows into the application logic 14 fromthe IN to the IN′ via the input test cell 12 i, and flows from theapplication logic from OUT′ to OUT via the output test cell 12 j. Thefollowing examples describe the sequence of control signals issued viathe control bus 17 to cause the test cells 12 i and 12 j to perform asample and an insert test operation at the boundary of the IC in FIG. 3during normal operation.

SAMPLE OPERATIONS SEQUENCE

[0056] 1) Initially both test cells are in Normal Mode and Idle Mode

[0057] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0058] (where BA equals the select control signals issued to the 4:1multiplexor 22)

[0059] Application Logic's IN′ input is driven by the IC's IN input

[0060] IC's OUT output is driven by the Application Logic's OUT′ output

[0061] Both test cells' D latches remain in their present state

[0062] Both test cells' D flip-flops remain in their present state

[0063] 2) Enter Load Mode for one CLK to capture input and outputboundary data

[0064] Control Bus: DMX=0, BA=01, HOLD=0, CLK=Active

[0065] Application Logic's IN′ input is driven by the IC's IN input

[0066] IC's OUT output is driven by the Application Logic's OUT′ output

[0067] Both test cells' D latches remains in their present state

[0068] Both test cells' D flip-flops clock in the logic level on theirODI input

[0069] 3) Enter Shift Mode for two CLKs to shift out captured data

[0070] Control Bus: DMX=0, BA=00, HOLD=0, CLK=Active

[0071] Application Logic's IN′ input is driven by the IC's IN input

[0072] IC's OUT output is driven by the Application Logic's OUT′ output

[0073] Both test cells' D latches remains in their present state

[0074] Both test cells' D flip-flops clock in the logic level on theirSDI input

[0075] 4) Enter Idle mode, test complete

[0076] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0077] Application Logic's IN′ input is driven by the IC's IN input

[0078] IC's OUT output is driven by the Application Logic's OUT′ output

[0079] Both test cells' D latches remains in their present state

[0080] Both test cells' D flip-flops remain in their present state

TEST DATA INSERT OPERATION SEQUENCE

[0081] 1) Initially both test cells are in Normal Mode and Idle Mode

[0082] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0083] Application Logic's IN′ input is driven by the IC's IN input

[0084] IC's OUT output is driven by the Application Logic's OUT′ output

[0085] Both test cells' D latches remain in their present state

[0086] Both test cells' D flip-flops remain in their present state

[0087] 2) Enter Shift Mode for two CLKs to load test data to insert

[0088] Control Bus: DMX=0, BA=00, HOLD=0, CLK=Active

[0089] Application Logic's IN′ input is driven by the IC's IN input

[0090] IC's OUT output is driven by the Application Logic's OUT′ output

[0091] Both test cells' D latches remains in their present state

[0092] Both test cells' D flip-flops clock in the logic level on theirSDI input

[0093] 3) Enter Idle Mode and update both test cells' D latches withtest data to insert

[0094] Control Bus: DMX=0, BA=11, HOLD=“0,1,0”, CLK=Active

[0095] Application Logic's IN′ input is driven by the IC's IN input

[0096] IC's OUT output is driven by the Application Logic's OUT′ output

[0097] Both test cells' D latches update to the logic level in the Dflip-flops

[0098] Both test cells' D flip-flops remain in their present state

[0099] 4) Remain in Idle Mode, set DMX high to insert test data

[0100] Control Bus: DMX=1, BA=11, HOLD=0, CLK=Active

[0101] Application Logic's IN′ input is driven by input test cells' Dlatch

[0102] IC's OUT output is driven by output test cells' D latch

[0103] Both test cells' D latches remain in their present state

[0104] Both test cells' D flip-flops remain in their present state

[0105] 5) Remain in Idle Mode, set DMX low to remove test data, testcomplete

[0106] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0107] Application Logic's IN′ input is driven by the IC's IN input

[0108] IC's OUT output is driven by the Application Logic's OUT′ output

[0109] Both test cells' D latches remain in their present state

[0110] Both test cells' D flip-flops remain in their present state

[0111] During test mode, the normal flow of input and output datathrough the test cells 12 i and 12 j is inhibited. In the test mode, theinput test cell 12 icontrols the IN′ input to the application logic andobserves the IN inputs to the IC. Likewise, the output test cell 12 jcontrols the OUT output from the IC 10 and observes the OUT′ output fromthe application logic. The following examples describe the sequence ofcontrol issued via the control bus to cause the test cells 12 i and 12 jto perform a boundary scan test and output buffer toggle operation.

BOUNDARY SCAN TEST OPERATION SEQUENCE

[0112] 1) Initially both test cells are in Normal Mode and Idle Mode

[0113] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0114] Application Logic's IN′ input is driven by the IC's IN input

[0115] IC's OUT output is driven by the Application Logic's OUT′ output

[0116] Both test cells' D latches remain in their present state

[0117] Both test cells' D flip-flops remain in their present state

[0118] 2) Enter Shift Mode for two CLKs to shift in the first outputtest pattern

[0119] Control Bus: DMX=0, BA=00, HOLD=0, CLK=Active

[0120] Application Logic's IN′ input is driven by the IC's IN input

[0121] IC's OUT output is driven by the Application Logic's OUT′ output

[0122] Both test cells' D latches remains in their present state

[0123] Both test cells' D flip-flops clock in the logic level on theirSDI input

[0124] 3) Enter Idle Mode, update D latches with first output testpattern

[0125] Control Bus: DMX=0, BA=11, HOLD=“0,1,0”, CLK=Active

[0126] Application Logic's IN′ input is driven by the IC's IN input

[0127] IC's OUT output is driven by the Application Logic's OUT′ output

[0128] Both test cells' D latches update to the logic level in the Dflip-flops

[0129] Both test cells' D flip-flops remain in their present state

[0130] 4) Remain in Idle Mode, enter Test Mode, apply first output testpattern

[0131] Control Bus: DMX=1, BA=11, HOLD=0, CLK=Active

[0132] Application Logic's IN′ input is driven by input test cells' Dlatch

[0133] IC's OUT output is driven by output test cells' D latch

[0134] Both test cells' D latches remains in their present state

[0135] Both test cells' D flip-flops remain in their present state

[0136] 5) Enter Load Mode for one CLK to capture input and outputboundary data

[0137] Control Bus: DMX=1, BA=01, HOLD=0, CLK=Active

[0138] Application Logic's IN′ input is driven by input test cells' Dlatch

[0139] IC's OUT output is driven by output test cells' D latch

[0140] Both test cells' D latches remains in their present state

[0141] Both test cells' D flip-flops clock in the logic level on theirODI input

[0142] 6) Enter Shift Mode for two CLKs to shift out captured data andshift in next output test pattern

[0143] Control Bus: DMX=1, BA=00, HOLD=0, CLK=Active

[0144] Application Logic's IN′ input is driven by input test cells' Dlatch

[0145] IC's OUT output is driven by output test cells' D latch

[0146] Both test cells' D latches remains in its present state

[0147] Both test cells' D flip-flops clock in the logic level on theirSDI input

[0148] 7) Enter Idle Mode, update D latches to apply next output testpattern

[0149] Control Bus: DMX=1, BA=11, HOLD=“0,1,0”, CLK=Active

[0150] Application Logic's IN′ input is driven by input test cells' Dlatch

[0151] IC's OUT output is driven by output test cells' D latch

[0152] Both test cells' D latches update to logic level to the Dflip-flops

[0153] Both test cells' D flip-flops remain in their present state

[0154] 8) Repeat steps 5 through 7 until boundary test is complete, thenissue control to return to Normal mode and Idle mode (Step 1)

OUTPUT BUFFER TOGGLE OPERATION SEQUENCE

[0155] 1) Initially both test cells are in Normal Mode and Idle Mode

[0156] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0157] Application Logic's IN′ input is driven by the IC's IN input

[0158] IC's OUT output is driven by the Application Logic's OUT′ output

[0159] Both test cells' D latches remain in their present state

[0160] Both test cells' D flip-flops remain in their present state

[0161] 2) Enter Shift Mode for two CLKs to shift in the output buffertoggle pattern

[0162] Control Bus: DMX=0, BA=00, HOLD=0, CLK=Active

[0163] Application Logic's IN′ input is driven by the IC's IN input

[0164] IC's OUT output is driven by the Application Logic's OUT′ output

[0165] Both test cells' D latches remains in their present state

[0166] Both test cells' D flip-flops clock in the logic level on theirSDI input

[0167] 3) Enter Idle Mode, update D latches with output test pattern

[0168] Control Bus: DMX=0, BA=11, HOLD=“0,1,0”, CLK=Active

[0169] Application Logic's IN′ input is driven by the IC's IN input

[0170] IC's OUT output is driven by the Application Logic's OUT′ output

[0171] Both test cells' D latches update to the logic level in the Dflip-flops

[0172] Both test cells' D flip-flops remain in their present state

[0173] 4) Remain in Idle Mode, enter Test Mode, apply output testpattern

[0174] Control Bus: DMX=1, BA=11, HOLD=0, CLK=Active

[0175] Application Logic's IN′ input is driven by input test cells' Dlatch

[0176] IC's OUT output is driven by output test cells' D latch

[0177] Both test cells' D latches remains in their present state

[0178] Both test cells' D flip-flops remain in their present state

[0179] 5) Enter Toggle Mode, Set HOLD input high, Toggle test begins(for “N” clock inputs)

[0180] Control Bus: DMX=1, BA=10, HOLD=1, CLK=Active

[0181] Application Logic's IN′ input is driven by input test cells' Dlatch

[0182] IC's OUT output is driven by output test cells' D latch

[0183] Both test cells' D latches pass data from D flip-flop to DOUToutput

[0184] Both test cells' D flip-flops clock in the Õ-D latch output

[0185] 6) Enter Idle Mode, Set HOLD and DMX input low, Toggle testcomplete

[0186] Control Bus: DMX=0, BA=11, HOLD=0, CLK=Active

[0187] Application Logic's IN′ input is driven by the IC's IN input

[0188] IC's OUT output is driven by the Application Logic's OUT′ output

[0189] Both test cells' D latches remain in their present state

[0190] Both test cells' D flip-flops remain in their present state

[0191] NOTE: In FIG. 3, it is desired not to toggle the input test cellduring the Toggle test, a separate HOLD input can be used to force theoutput of the input test cell to be static while the output test celltoggles. Likewise separate control (A and B) can cause the input testcell into an Idle mode while the output test cell is toggling.

[0192] Referring now to FIG. 4a, a block diagram of a preferredimplementation of a bidirectional test cell 30 is illustrated. Thebidirectional test cell 30 may be used in connection with aninput/output pin, through which signals may flow in both directions. Thebidirectional cell 30 uses the test cell 12 illustrated in FIG. 2 as abase cell, adding additional circuitry to provide bidirectionaloperation. Specifically, the bidirectional cell 30 provides threeadditional multiplexers 32, 34 and 36. The first multiplexer 32 has twoinputs SYSG (the system tristate enable) and TSTG (the test tristateenable). The multiplexer is controlled by a SELG (select enable) signal,which selects one of the two inputs. The output of the first multiplexer32 is the OBG (output buffer tristate enable). The OBG signal controlsthe output state of the IC's tristate output buffer.

[0193] The second multiplexer 34 receives two inputs, a DINA signal anda DINB signal. The multiplexer 34 is controlled by the output of themultiplexer 32, the OBG signal. The DINA input is an output from theIC's application logic 14 and the DINB input is the external input fromthe I/O buffer. The OBG signal output from the multiplexer 32 is used toselect between inputs of the multiplexer 34.

[0194] The third multiplexer 36 has two inputs, DINA and thenon-inverted output (LÕ) from the latch 26 of the base test cell 12.This third multiplexer 36 is controlled by the DMX signal.

[0195] The output of the second multiplexer 34 is connected to the ODIinput of the base test cell 12. The output of the third multiplexer 36is denoted as DOUTA and the DOUT signal from the base test cell 12 isdenoted as DOUTB.

[0196] In operation, the OBG output is driven by the SYSG input (normalmode tristate control input) when the SELG input is low. When the SELGinput is high, the OBG output of the first multiplexer 32 is driven bythe TSTG input (test mode tristate control input). In FIG. 4a, it isassumed that a low output on the OBG signal will cause an output bufferto be active and high output on the OBG signal will cause an outputbuffer to be tristate.

[0197] The second multiplexer 34 is controlled by the OBG output fromthe first multiplexer 32. The purpose of the second multiplexer is tocouple one of the two data inputs, DINA or DINB, to the ODI input of thebase test cell, to allow the appropriate signal to be sampled during aload operation. The DINA input to the second multiplexer 34 is an outputfrom the application logic. When the second multiplexer's select inputOBG is set low, indicating an output operation from the applicationlogic, the DINA signal is coupled to the ODI input of the base test cell12 and can be sampled during a load operation. When the secondmultiplexer's select input OBG is set high, indicating an inputoperation to the application logic, the DINB signal is coupled to theODI input of the test cell 12 and can be sampled during a loadoperation. The third multiplexer 36 is controlled by the DMX signal,also sent to the test cell 12. The LÕ output of the test cell 12 is theoutput of the D latch 26 inside the test cell 12. The LÕ output allowsholding the DOUTA output signal constant in test mode during load andshift operations. When the DMX input to the test cell 12 and thirdmultiplexer 36 is set low, the bidirectional cell 30 is in normal mode.In the normal mode, the DINA output passes through the third multiplexer36 and is output from the cell via the DOUTA output, establishing thenormal data output path from the application logic 14 to the outputbuffer section of an I/O buffer. Likewise, in the normal mode, the DINBinput passes through the 2:1 multiplexer 28 within the test cell 12 andis output from the cell via the DOUTB output, establishing the normaldata input path from the input buffer section of an I/O buffer to theapplication logic 14.

[0198] When the DMX input to the test cell 12 and third multiplexer 36is set high, the bidirectional test cell 30 is placed in the test mode.In the test mode, the test cell LÕ test data output passes through thethird multiplexer 36 is output from the scope cell via the DOUTA output,establishing the test data output path from the test cell 12 to theoutput buffer section of an I/O buffer. Likewise, in the test mode, theinternal test cells LÕ test data output passes through the test cell'sinternal 2:1 multiplexer 28 and is output from the test cell 12 via theDOUTB output, establishing the test data output path from the test cellto the application logic 14.

[0199] In FIG. 4b, a block representation of bidirectional test cell 30is shown connected between a bidirectional buffer and application logic14. When a data output operation is performed, the output buffer 38 isenabled by OBG. In the normal mode, the data from the application logic14 enters the bidirectional test cell 30 via the DINA input, passesthrough the bidirectional test cell 30 and is coupled to the outputbuffer 38 via the DOUTA output. The DOUTA output passes through theoutput buffer 38 and is applied to the I/O pin 40. In test mode, thetest data stored in the bidirectional test cell 30 is supplied to theoutput buffer via the DOUTA output, passes through the output buffer 38and is applied to I/O pin 40.

[0200] When a data input operation is performed, the output buffer isplaced in a high impedance state by the OBG signal. In normal mode, thedata from the I/O pin 40 enters the bidirectional test cell 30 via theinput buffer 41 and the DINB input, passes through the test cell 30, andis applied to the application logic via the DOUTB output. In test mode,the test data stored in the test cell 30 is applied to the applicationlogic by the DOUTB output.

[0201] Referring now to FIG. 5, there is shown a schematic diagramrepresenting a particular implementation of the test cell 12. Theimplementation comprises multiplexers 22 and 28, D flip-flop 24 andlatch 26.

[0202] The first multiplexer 22 has six independent input signals. TheSDI signal is input to two cascaded inverters 108 and 110. The resultingoutput from inverter 110 is then input to a transmission gate 112. Atransmission gate is formed by tying both the sources and drains of a Pchannel transistor to an N channel transistor. The output oftransmission gate 112 is tied to the output of transmission gate 114 andto the input to transmission gate 116. The output of transmission gate116 is likewise tied to the output of transmission gate 122 and to theinput to a pair of cascaded inverters 118 and 120. This output atinverter 120 represents the final output from multiplexer 22.

[0203] The ODI input to multiplexer 22 is connected to transmission gate114. The output of transmission gate 114 is tied to the output oftransmission gate 112 and to the input to transmission gate 116.

[0204] A third input to multiplexer 22 is the inverted output of latch26. This signal is input into transmission gate 124. The output oftransmission gate 124 is tied to the output of transmission gate 126 andto the input to transmission gate 122.

[0205] A fourth input to multiplexer 22 is the output of the D flip-flop24. This signal is input to transmission gate 126. The output oftransmission gate 126 is then tied to the output of transmission gate124 and to the input to transmission gate 122. The resultant output fromtransmission gate 122 is then tied to the output transmission gate 116.

[0206] The two remaining inputs of multiplexer 22 act as select signalsfor the various transmission gates within the multiplexer 22. Inputsignal A is first connected to inverter 128. The output of inverter 128is then connected to the input of inverter 130. Additionally, the outputof inverter 128 is further connected to the P channel gate oftransmission gates 114 and 126. The same output is connected to the Nchannel gate of transmission gates 112 and 124. The output of inverter130 is connected to the P channel gate of transmission gates 112 and 124and the N channel gate of transmission gates 114 and 126.

[0207] The B input to multiplexer 22 is also used as a select signal.The B input is connected to inverter 132. The output of inverter 132 isconnected to inverter 134. Additionally, the output of inverter 132 isconnected to the P channel gate of transmission gate 122 and the Nchannel gate of transmission gate 116. The output of inverter 134 isconnected to the N channel gate of transmission gate 122 and the Pchannel gate of transmission gate 116.

[0208] The D flip-flop 24 is connected to both a clock input CLK and theoutput of multiplexer 22. Within the D flip-flop 24, the clock signal isinput to inverter 140, whose output is used to control the gate of Nchannel transistor 142. The clock signal is also used to control thegate of N channel transistor 144. The D input of D flip-flop 24 isconnected to the first source/drain of N channel transistor 142. Thesecond source/drain of transistor 142 is connected to the input ofinverter 146. The output of inverter 146 is connected to the firstsource/drain of N channel transistor 144 and also to the input ofinverter 148. The output of inverter 148 is connected to the input ofinverter 146. The second source/drain of transistor 144 is connected tothe input of inverter 150. The output of inverter 150 is connected bothto the input of inverter 152 and the input of inverter 154. The outputof inverter 154 is connected to the input of inverter 150 The output ofinverter 150 is also connected to the input of the transmission gate126. The output of inverter 152 is the inverted output of the Dflip-flop 24. The inverted output of D flip-flop 24 is then input toinverter 156. The output of inverter 156 is the SDO output of the testcell.

[0209] The output of D flip-flop 24 (output of inverter 150) isconnected to the D input of latch 26. This input is connected to thefirst source/drain of N channel transistor 160. The second source/drainof N channel transistor 160 is connected to the input of inverter 162.Within latch 26, the output of inverter 162 is connected to the input ofinverter 166 and inverter 164. The output of inverter 166 is connectedto the input of inverter 162. The output of inverter 162 also representsthe inverted output of latch 26. As mentioned above, this invertedoutput is connected to multiplexer 22 through transmission gate 124. Theoutput of inverter 164 represents the non-inverted output of the latch26, which is connected to multiplexer 28. The latch 26 is alsocontrolled by a hold voltage input to the base of N channel transistor160.

[0210] The second multiplexer 28 within the test cell has three separateinputs, DIN, the output of inverter 164, and DMX. The DIN signal isconnected to the one gates of P channel transistor 170 and N channeltransistor 172. The output of inverter 164 is connected to the gate of Pchannel transistor 182 and N channel transistor 184. The DMX input isconnected to the gates of N channel transistor 174, 176 and 178, andalso to the gate of P channel transistor 180. The first source/drain ofN channel transistor 178 is connected to V_(cc) while the secondsource/drain is connected to node 196. Similarly, the first source/drainof N channel transistor 176 is connected to ground while the secondsource/drain is connected to node 196. Node 196 is further connected tothe gate of P channel transistor 188 and the gate of N channeltransistor 186. The first source/drain of P channel transistors 188 and180 are tied and connected to V_(cc). The second source/drain of Pchannel transistors 188 and 180 are connected to the first source/drainof P channel transistors 182 and 170, respectively. The secondsource/drain of P channel transistors 182 and 170 are tied and connectedto node 194. The first source/drain of N channel transistors 184 and 172are tied and are further connected to node 194. The second source/drainof N channel transistors 184 and 172 are connected to the firstsource/drain of N channel transistors 174 and 186, respectively. Thesecond source/drain of N channel transistors 174 and 186 are connectedto ground. Node 196 is also connected to the gates of N channeltransistors 192 and 190. The first source/drain of N channel transistor192 is connected to V_(cc). The second source/drain of N channeltransistor 192 is connected to the first source/drain of N channeltransistor 190 and this combined signal represents the DOUT signal ofthe test cell. The second source/drain of N channel transistor 190 isconnected to ground.

[0211] The present invention retains high speed performance on theobservability data input (ODI), maintains a zero hold time on the shiftdata input (SDI), increases the setup time on SDI and increases thepropagation delay from the clock transition to the SDO output. A zerohold time on SDI eliminates any abnormal data propagation problem in acascaded configuration. A large setup time on SDI and a slight increaseon the clock-to-Õ delay enhances the clock skew margin to eliminatepropagation errors due to skew between the various components of thetest cell.

[0212] Two weak inverters 108 and 110 are used in the first multiplexer22 in order to slow the serial data input and therefore increase thesetup time. Since these inverters apply only to the SDI input, noperformance degradation to the ODI input is introduced by this method.Another two inverters 150 and 152 are inserted in the output path of SDOto slightly increase the clock-to-Õ propagation delay. A SPICEcharacterization shows that the invention has min/max SDI setup of 2/14nanoseconds, a zero SDI hold time and min/max clock-to-Õ delay of0.96/5.96 nanoseconds. This data leads to a min/max clock skew margin of2.96/19.96 nanoseconds.

[0213] The test cells of the present invention provide significantadvantages over the prior art. First, the test cell of the presentinvention may be used to perform internal and external boundary testingsimultaneously in order to reduce overall test time. Second, the testcells are capable of sampling or inserting data at the boundary duringnormal operation of the host integrated circuit. Third, the test cell issynchronous in operation with a free running test clock. Fourth, thepresent invention provides a method of toggling an IC's output buffers,independent of the IC's application logic, in order to achieveparametric measures and to facilitate boundary tests. Fifth, the testcell provides self-testing capability.

[0214] The functionality of the test cell 12 of the present inventionmay be enhanced through the use of cell libraries, in which additionalcircuitry may be provided on one or more of the test cells 12 used in IC10 to provide an enhanced test circuit. A library of such circuits maybe provided to enable a circuit designer to customize a particular IC10.

[0215] Referring to FIG. 6, a maskable comparator logic section 200 isshown in connection with the test cell 12 of the present invention. Themaskable comparator logic section 200 adds comparability test featuresfor effectuating a test in response to a condition.

[0216] The maskable comparator logic section 200 comprises XOR gate 202and a NAND 204. The XOR gate 202 has two inputs: a first input connectedto the DIN and ODI inputs to the test cell 12 and a second inputconnected to an expected data (EXPD) signal. The NAND 204 also has twoinputs: one input connected to the output of the XOR gate 202 and asecond input connected to a compare mask (CMPMSK) signal. The output ofthe NAND gate 204 provides a compare output (CMPOUT) signal.

[0217] The maskable comparator logic 200 provides a means to comparelogic level appearing at the DIN input of the test cell 12 against apredetermined logic level appearing at the EXPD input. If the logiclevel on the DIN input and the EXPD input match, the output of theexclusive OR gate will driven low. If the logic level on the DIN inputand the EXPD input do not match, the output of the exclusive OR gatewill be driven high. A low level output (match condition) from theexclusive OR gate will cause the NAND gate to output a high level viathe CMPOUT output. The high level output (no match) from the exclusiveOR gate 202 will cause the NAND gate 204 to output a low logic level viathe CMPOUT output, unless the CMPMSK input to the NAND gate 204 is at alow level.

[0218] A high logic level on the CMPOUT output of the comparator logicsection 200 indicates that the input or output boundary signal passingthrough this particular test cell is equal to an expected condition. Byhaving similar test cells at every input and output signal of anintegrated circuit, along with logic to detect the condition where allthe CMPOUT signals from the various test cells are high, it is possibleto detect the occurrence of an expected boundary condition over theentire range of an integrated circuit's inputs and outputs.

[0219] In some boundary compare applications, the condition of one ormore of the integrated circuits inputs and/or outputs may be irrelevant.In these circumstances, the comparator logic 200 may be forced to maskoff the compare operation and output a high level on the CMPOUT outputregardless of the result of the compare operation. This capabilityallows for “Don't Care” comparison conditions to be set around theboundary of an integrated circuit design. The Don't Care condition isachieved by setting the CMPMSK of a particular test cell to a low logiclevel. All test cells having a low level applied to their CMPMSK inputwill output a high logic level from their CMPOUT output. By forcing theCMPOUT output high, the test cells with Don't Care conditions do notinfluence the overall result of a comparison taking place in other testcells at the boundary of an integrated circuit.

[0220] In some applications, the test cells may be required to providePseudo-Random Pattern Generation (PRPG) and/or Parallel SignatureAnalysis (PSA) capabilities at the boundary of an integrated circuit tofacilitate testing. In the PRPG mode, a series of seriallyinterconnected test cells can be made to generate a pseudo-random outputpattern seqence from the DOUT outputs. In the PSA mode, a series ofserially interconnected test cells can be made to compress the dataappearing at the DIN input into a “signature” for testing purposes.

[0221] A preferred implementation of a library cell capable ofimplementing PSA test logic is shown in FIG. 7. The inputs and output ofthe base test cell 12 comprises the signals described in connection withFIG. 2. Additionally, the PSA logic section 206 receives two inputsignals, Data Mask (DATMSK) and PSA Enable (PSAENA). The DATMSK andPSAENA inputs are extensions of the control bus.

[0222] The PSA logic section 206 comprises an Exclusive OR gate 208 andtwo NAND gates, 210 and 212. The NAND 210 is connected to the DATMSKsignal and the DIN input signal. The NAND gate 212 is connected to thePSAENA signal and the SDI signal. The outputs of the NAND gate 210 and212 are connected to the inputs of the Exclusive OR gate 208. The outputthe Exclusive OR gate is connected to the ODI input of the base testcell 12.

[0223] When the PSA logic section 206 is attached to the base cell 12,the normal connection of the ODI input to the DIN input is modified suchthat it is no longer a direct interconnect. However, the base functionof capturing test data during a load operation via the ODI input isstill valid, but addition rules set forth below and signal routing isrequired to accommodate the load operation via the PSA test logic. Allother functions (idle, shift and toggle) and their required cell to cellinterconnects remain the same.

[0224] To achieve the basic load operation, the DATMSK and PSAENA inputsto the logic section 206 are set to a high and low logic level,respectively. In this condition, the PSA logic section provides arouting path from the DIN input, through the NAND gate 210 and theExclusive OR gate 208 to the ODI input of the base test cell 12. Whenthe load operation is issued, the test cell 12 captures the logic levelon the DIN input via the routing channel through the PSA logic section206.

[0225] When a PSA operation is to be performed by the test cell, theMSKDAT and PSAENA inputs are both set to a high logic level and controlis issued to the base test cell 12 to perform a load operation. With theMSKDAT and PSAENA inputs set in this manner, the PSA logic section 206performs an Exclusive OR operation on the logic levels present on theDIN and SDI inputs, and outputs the result to the ODI input of the testcell 12. During the load operation, the test cell 12 samples the ODIinput, storing the result of the Exclusive OR operation. The localExclusive OR and load operation performed in each test cell 12, incombination with the required cell to cell interconnect for serialshifting (i.e., the SDI of one cell connected to the SDO of another) andpolynomial feedback, forms the basis from which a boundary scansignature analysis structure can be implemented.

[0226] During a PSA operation, the PSA logic section 206 provides ameans to mask off the effect of the DIN input on the Exclusive ORoperation. The masking is achieved by setting the MSKDAT input low whileleaving the PSAENA input high. When the MSKDAT input is set low, the PSAlogic section 206 couples the SDI input to the ODI input of the testcell 12 and only the value of a preceding cell's SDO output is sampledand stored in the test cell 12. This capability allows masking out thesignal attached to the DIN input of one or more of the test cells duringa PSA operation at the boundary of an integrated circuit.

[0227] When a PRPG operation is to be performed by the test cell,control is issued to cause the test cell 12 to perform a shift operationfrom the SDI input to the SDO output.

[0228] During PRPG, data is shifted through a series of test cells 12 toproduce a pseudo random output pattern. The resulting pseudo randompattern generation output is determined by the length of the scan pathand the polynomial feedback connections of the test cells 12 in the scanpath. Also, the hold and DMX inputs to the test cell will be set high,allowing the generated test signal to be driven out of the test cell'sDOUT output.

[0229] In applications using test cells with PRPG and/or PSA testfeatures, it is beneficial to provide a Programmable Polynomial Tap toallow the adjusting the polynomial feedback connection between the testcells 12 to suite a particular group or range of test cells at theboundary of an integrated circuit. The advantages of including thisfeature are: (1) simplification of the implementation of test cells inan integrated circuit design, (2) elimination of the need to addexternal polynomial tap capability, and (3) improvement of the placementand signal routing of test cells in an integrated circuit layout, sinceall the required logic is resident within each test cell 12.

[0230] The preferred implementation of a test circuit comprising a basetest cell 12, PSA logic section 206 and a Programmable Polynomial Tap214 is shown in FIG. 8. The inputs and outputs to the test cell 12 andthe PSA logic section are the same as shown in FIG. 7. The ProgrammablePolynomial Tap logic section 214 requires two additional input signals,Polynomial Tap Enable (PTENA) and Feedback Input (FBI), and oneadditional output signal, Feedback Output (FBO). The PTENA signal is anextension of the control bus. The FBI and FBO signals provide theinterconnect between test circuits for implementing the polynomialfeedback network, required for the PRPG and/or PSA test operations. TheProgrammable Polynomial Tap logic section comprises an Exclusive NORgate 216 and a NAND gate 218. The NAND gate receives the SDO output ofthe associated test cell 12 and the PTENA signal as input. The ExclusiveNOR gate 216 receives the output of the NAND gate 218 and the FBIsignal. The output the Exclusive NOR gate 216 is the FBO signal.

[0231] A key capability required to perform PRPG or PSA is to provide afeedback network which is based on the Exclusive OR of the logic statein all or a selected group of test circuits in scan path. The result ofthis feedback network is input to the first test circuit in the scanpath to close the feedback loop. In FIG. 8, the combination of the NAND218 and Exclusive NOR gate 216 provide the capability to include orexclude the logic state of the particular test circuit in the feedbacknetwork.

[0232] Test circuits, having similar Programmable Polynomial Tap logicsections may be interconnected together as shown in FIG. 9a. Four testcircuits 220 a-d having PRPG/PSA logic sections and ProgrammablePolynomial Tap logic sections are interconnected in the scan path fromthe primary serial data input (PSDI) to the Primary Serial Data Output(PSDO) signal. The Programmable Polynomial Tap logic of each test cell220 a-d is interconnected in such a way that a trailing test circuit'sFBO output signal supplies the input for a leading test circuit's FBIinput. For example, the FBO of test circuit 220 c is connected to theFBI of test cell 220 b. The PTENA input for each test circuit 220 a-d isapplied via the PTENA bus. A feedback select (FBSEL) input (an extensionof the control bus 17) controls a multiplexer 222 at the input of thefirst test circuit 220 a which feeds the SDI input of the test circuit220 a. The FBI input of the last test circuit 220 d is wired to a lowlogic level so that it have no effect on the Programmable polynomial Taplogic of the last test circuit 220 d.

[0233] During normal shift operations, serial data enters PSDI and flowsthrough the test cells and out PSDO. When placed in the PRPG or PSAmode, the multiplexer 222 at the input of first test circuit 220 aselects the feedback result (FBR) signal to be connected to the SDIinput of the first test circuit 220 a. The Programmable Polynomial Taplogic in the test circuits 220 a-d, in combination with the FBI and FBOwiring interconnects, forms the Exclusive OR feedback network requiredfor PRPG and PSA operations. If the PTENA input of a test circuit ishigh, the logic state of test cell 12 of that test circuit 220 isincluded in the feedback network. If the PTENA input to a test circuitis low, the logic state of the test cell 12 of that test circuit is notincluded in the feedback network.

[0234] In some application it may be necessary to partition a primaryscan path, consisting of a series of test cells 12, each having PRPG/PSAand Programmable Polynomial logic, into sections. Each section of theprimary scan path may be configured as shown in FIG. 9b to providemultiple localized PRPG/PSA test functions within the primary scan path.Each section of the scan path has a feedback connection as shown in FIG.9a to allow selecting the appropriate test cells 12 in the scan pathsection to be included in the local feedback network. The FeedbackResult (FBR) of each local feedback network is coupled up to the firsttest cell 12 in a scan path section, via a multiplexer.

[0235] The PSA test logic may also be included in the bidirectional testcell of FIG. 4. The inclusion of the PSA test logic provides the samebenefits to bidirectional test cells as described in the unidirectionalcase.

[0236] A preferred implementation of a test circuit comprising a basetest cell 12, bidirectional multiplexer logic and a PSA logic section206 is shown in FIG. 10. The input and output signals required for thistest circuit are the same as those used in connection with FIGS. 4 and7. The only change required to create the bidirectional test circuitwith PSA logic is to insert the PSA logic and make the following wiringconnections: (1) connect the SELODI output of the second multiplexer 34up to the input of PRPG/PSA NAND gate 210 shown connected to DIN in FIG.7, (2) connect the SDI input attached to the test cell up to the inputof PRPG/PSA NAND gate 212 as shown in FIG. 7, and (3) connect the outputof PRPG/PSA exclusive OR gate 208 up to the ODI input of the test cell12.

[0237]FIG. 11 illustrates a bidirectional test circuit having both aPRPG/PSA logic section 206 and a Polynomial Tap logic section 214. Thecircuit of FIG. 11 is identical to the circuit of FIG. 10 with theadditional Polynomial Tap logic section 214 connected to test cell 12 asillustrated in connection with FIG. 8. Similarly, other combinations oflibrary cells are available for the bidirectional test circuit, such asa bidirection test circuit including maskable compare logic or abidirectional test circuit including maskable compare logic, PRPG/PSAlogic and polynomial tap logic.

[0238] While the cell library of the present invention has beendiscussed in connection with the base test cell 12 of FIG. 2, theconcept could be used with a base test cell 12 having anotherarchitecture. The library cells provide a integrated circuit designerwith a range of bit slice testability cells that can be used toconstruct a variety of different integrated circuit test structures. Theadvantages of providing test solutions in the form of library cells are:(1) simplification of the implementation of test architectures inintegrated circuit designs, (2) providing structured test methodologiesthat can be automated, (3) elimination of the need to construct ad-hoctest approaches for every new integrated circuit design, (4) improvementof placement and signal routing of test architectures, since allrequired test logic is resident within the test circuits and, (5)providing the customer with a basis from which desired testabilityfeatures may be selected.

[0239] To facilitate testing at the IC through system level, standardoff-the-shelf components, such as registers, latches, buffers ortransceivers, may be designed to include a test interface and a boundaryscan path comprised of test cells 12. Implementing test circuitry intostandard components for the purpose of simplifying test at higher levelsof assembly provides a method of reducing the cost to test and maintainhardware systems.

[0240] Today, the testing of circuit boards and systems requires the useof expensive test equipment and mechanical probing techniques. In orderto test a board residing in a system, it must be removed so that testaccess to test equipment is available.

[0241] Standard components with embedded test circuitry that isaccessible via a serial test interface, simplifies testing. A boarddesign which uses such parts can be tested while it remains in thesystem, via the serial test bus. Also such devices allow testing to beperformed with simpler, less expensive test equipment. In addition, withstate of the art board designs, it may not be physically possible toprobe a circuit because of the component density. In this case testingmay only be performed via the test circuitry embedded in the components.

[0242]FIG. 12 illustrates a situation where combinational logic 224 isbeing observed and controlled by test partitioning devices 226 and 228.The test partitioning devices 226 and 228 could be based on a number ofwell-known devices such as buffers, latches, registers or transceivers.For purposes of illustration, it is assumed that the partitioningdevices 226 and 228 are 8-bit registers. The combinational logic maycomprise any number of circuits without in-circuit testing ability.

[0243] The input test register 226 may observe the data which wouldotherwise be sent to the combinational logic, and may output data tocontrol the combinational logic 224. The output test register 228 mayobserve the data output from the combinational logic 224 and may controlthe output to devices which would otherwise be connected to the outputof the combinational logic 224. Serial data is received by the inputtest register 226 which outputs serial data to the output test register228. By observing inputs and controlling outputs, the test register 226and 228 may test the combinational logic 224 in much the same way aspreviously described in connection with FIG. 1.

[0244]FIG. 13 illustrates an embodiment of a test device 226. Datainputs DO-7 are input to the test device 226 through input buffer 230.The output of input buffer 230 is connected the an input test circuitregister (input TCR) 232. The output of the test circuit register 232 isconnected to a register 234. The output of the register 234 is connectedto an output test circuit register (output TCR) 236. The output of theoutput TCR 236 is connected to an output buffer 238, which provides theoutput data signals ÕO-7. Test cells 240 and 242 receive control signalsfrom outside the device. In this case, test cell 242 receives a clockinput (CLK) and test cell 240 receives a control input (OC). The outputof test cell 240 is connected to the output buffer 238 for tri-stateoperation. The output of test cell 242 is connected to the clock inputof register 234. The SDI signal from outside the test device 236 isreceived by the test cell 240, a scan bypass register 244 and aninstruction register 246. A scan data path exists through the test cell240, test cell 242, the input TCR 232 and the output TCR 236. Serialdata output of the output TCR 236 is connected to a multiplexer 248along with the output of the scan bypass 244. The multiplexer 248receives a scan path select signal from the instruction register 246.The output of the multiplexer 248 is connected to a multiplexer 250along with an output from the instruction register 246. The multiplexer250 also receives a select signal from a test port 252. The test portreceives MODE and clock (CLK) signals from outside the test device 226and outputs scan and test control signals. The instruction register 246also outputs test, control signals to the test cells 240 and 242 andTCRs 232 and 236.

[0245] It should be noted that the control signals (CLK and OC) input tothe test register are exemplary, and other signals may be used for aspecific application. For example, a clear signal or an enable signalcould be connected through a test cell to a suitably designed register.Also, the register could be replaced by appropriate circuitry toimplement a latch, buffer, transceiver or other device. Also, the numberof control and data I/O signals may change depending on theimplementation of the device.

[0246] The scan structure of the test device 226 comprises a boundaryscan path (through the test cells 240 and 242 and TCRs 232 and 236), ascan bypass path and an instruction scan path. A scan access protocolissued via the MODE and SCK inputs allows serial data to be scanned intoeither the boundary or bypass scan path, or the instruction register.The selection between the boundary or bypass scan path is determined bythe current instruction residing in the instruction register, via thescan path select output to multiplexer 248.

[0247] The TCRs 232 and 236 comprise a plurality of test circuits basedon the test cell 12, as discussed previously. Typically, the TCRs 232and 236 will be formed from a plurality of test circuits with PRPG/PSAand/or programmable polynomial tap logic sections. The test cells 240and 242 are typically base test cells 12 without additional circuitry.The control circuitry to the test cells 240 and 242 and TCRs 232 and 236is not shown; however, a control bus would be connected to each cell forserial data shifting and test circuit control.

[0248] Test instructions may be scanned into the instruction register246 to cause the boundary scan logic to perform a test operation. If atest is not being performed, a normal operation instruction is scannedinto the instruction register 246. During a normal operationinstruction, the boundary scan logic allows normal I/O and controlsignals to flow freely through the boundary scan logic.

[0249] A “boundary scan instruction” may be installed in the instructionregister to allow the boundary scan path (through the TCRs 232 and 236and the test cells 240 and 242) to take control of the internal I/Osignals. This control is accomplished by setting the DMX input of theboundary scan cells to a high logic level. In this mode, externalcontrol can be issued by the MODE and SCK input to cause the boundaryscan path to capture the logic level on the DIN inputs of the test cells240 and 242 and TCRs 232 and 236. During the capture operation, the testcells 240 and 242 and input TCR 232 capture the state of the externaldata outputs (DO-7) and control inputs. Also during the captureoperation, the output TCR 236 captures the state of the internal logic234. After the data has been captured, additional external control isinput via MODE and SCK inputs to cause the boundary scan path to shiftout the captured data for inspection via the SDO pin.

[0250] While the captured data is shifted out, a test control pattern isshifted into the boundary scan path via the SDI input. During thecapture and shift operation, the DOUTs will remain in their presentstate because the HOLD input thereto will be set low. If not heldconstant, the ripple effect at the output could upset external logicattached to the outputs of the device.

[0251] When the shifting in and out of the boundary scan path iscomplete, additional external control is input via the MODE and SCKinputs to cause the previously installed control pattern to be appliedfrom the latches 26 of the various test cells and TCRs 240, 242, 232 and236. The process of capturing the boundary scan path inputs, followed byshifting out the captured data for inspection while shifting in the nexttest control pattern to be applied from the boundary scan path outputsis repeated until the desired level of testing is complete. In this way,the interior logic and external wiring interconnects and/or aneighboring ICs may be simultaneously tested.

[0252] A “boundary data sample instruction” may be installed in theinstruction register 242. The boundary data sample instruction allowsdata and control to pass freely through the boundary scan path while theSCK and MODE inputs cause the boundary scan path to capture the logicstate existing at their inputs. Once the boundary data has beencaptured, additional external control is issued via the SCK and MODEinputs to cause the boundary scan path to shift out the captured datafor inspection via the SDO pin.

[0253] A “control outputs to high impedance state instructions” allowsthe output buffers (ÕO-7) to be placed in a high impedance state.Although the outputs are in a high impedance state, the inputs remainfunctional and data and control inputs still affect the internal logic234. During this instruction, the scan bypass register (a singleflip-flop) is coupled to the SDI and SDO pins, to form a single bit scanpath through the test device during data register scan operations.

[0254] The benefit of this instruction is to place the outputs in atristate condition, which allows an external test probe to be applied tocontrol the outputs to a logic 1 or 0. Also, the abbreviated data scanpath through the scan bypass flip-flop allows reducing the internal scanpath length to a single bit.

[0255] A “control boundary outputs to a logic 1 or 0 instruction” allowsthe boundary scan path to take control of the I/O signals in order toapply a prescanned test control pattern from the outputs of the testcells 240 and 242 and TCRs 232 and 236. Prior to performing this testinstruction, the boundary scan path will have been scanned to installthe test control output pattern to be applied by the instruction. Duringthis instruction, the scan bypass register is coupled to the SDI and SDOpins in order to form a single bit scan path through the test deviceduring data register scan operations.

[0256] The benefit of this instruction is to allow the test device tooutput a particular pattern while testing is being performed on otherdevices connected to the test device output, such as the combinationallogic 224. Also, the abbreviated data scan path through the scan bypassflip-flop during instruction allows the internal scan path length to bereduce to a single bit.

[0257] The input and output TCRs 232 and 236 may be instructed tooperate synchronously with the external applied SCK input to provideadditional testing capabilities. The benefit of these test operations isthat no scanning is required during the test operation, thus reducingthe test time significantly.

[0258] The PSA operation is discussed in detail in connection with FIG.7. The input TCR 232 may perform the PSA operation either by itself orin conjunction with the output TCR 236. A circuit showing the input andoutput TCRs 232 and 236 used in conjunction to provide a 16-bit widesignature (assuming 8-bit TCRs) is illustrated in FIG. 14. Dataappearing at the data input is summed with the present state of theinput TCR 232 and is clocked into the input TCR 232 by the PSA/PRPG testclock signal output from the AND gate 253. During a PSA operation, theinput TCR 232 is placed in the load mode and the output TCR 236 isplaced in a shift mode and acts as an 8-bit shift register extension tothe input TCR 232. By combining the input TCR 232 with the output TCR236, a 16-bit wide signature of the 8-bit data input bus is available.Using a 16-bit PSA circuit, the number of input data patterns that canbe compressed into the input TCR 232 is increased from 255 to 65,535.During PSA operations, the data output (ÕO-7) from the output TCR 236 isfixed to a predetermined pattern, so that the rippling data during PSAis not propagated out to the combinational logic 224.

[0259] The clocking for PSA comes from a gating circuit shown in FIG.14. When the PSA instruction is installed and the external control hasplaced the test port 252 in an idle state, the gating signals areadjusted to allow the AND gate 253 to pass the SCK input to the TCRs 232and 236. The instruction register 246 outputs a test clock enable signalwhen the instruction is installed. The test port 252 outputs a syncsignal when it enters a non-scanning idle state. When both enablesignals are set high, the external SCK is gated through the AND gate 252to produce the PSA/PRPG test clock.

[0260] At the end of a PSA instruction, the external control (SCK andMODE) will cause the test port 252 to inhibit the PSA/PRPG test clockand a new instruction will be scanned into the instruction register 246.After the scan path is set back to its normal configuration, thesignature stored in the TCRs 232 and 236 can be scanned out forinspection via a boundary scan read instruction, explained hereinbelow.

[0261] Similarly, a PRPG instruction may be installed in the instructionregister 246 to provide output pattern generation. Once again, the TCRs232 and 236 may be combined to provide a 16-bit wide pattern generationcapable extending the number of 8-bit output patterns. The 16-bitconfiguration is similar to that shown in FIG. 14. During a PRPGoperation, both TCRs are placed in a shift mode. The pattern generationis output from the output TCR 236. Clocking for PRPG is identical tothat described in the PSA instruction. Similarly, a new instruction willbe scanned into the instruction register at the end of a PRPG operationto reset the test clock enable bit and re-configure the boundary scanpath to its normal routing path.

[0262] As shown in connection with FIG. 15, PSA and PRPG may be runsimultaneously. In this configuration, the input and output TCRs 232 and236 are not combined, but rather fed back into themselves. Localmultiplexers 254 and 256 provide the required feedback connections tothe TCRs 232 and 236 respectively. Since the TCRs cannot be linkedtogether in this configuration, the PSA and PRPG operations are limitedto 8-bits. The clocking for the PSA and PRPG operations is identical tothat described in connection with the PSA instruction.

[0263] Similar in configuration to the simultaneous PSA and PRPGinstruction in FIG. 15, a simultaneous PSA and binary count up patternoutput instruction may also be performed. During this instruction, theinput TCR 232 performs PSA and the output TCR 236 outputs a binary countup pattern. The clocking for the PSA and binary count up patternoperations is identical to that described in connection with the PSAinstruction. The binary count up pattern is useful in providing binaryaddress patterns during memory testing. During this instruction a memorydevice's address may be stimulated by the count up pattern from a TCR236 of one test register while its data output is compressed by a TCR232 of another test register. A similar test application would beperformed by a PSA and PRPG instruction.

[0264] In FIG. 16 the test cells 12 of TCR 236 are shown attached to aCount Enable Logic section 258 to allow a binary count up pattern to beoutput from TCR 236. The count enable logic 258 comprises a plurality ofAND gates 260. Each AND gate 260 receives the output of the previous ANDgate as one input and the DOUT signal from an associated test cell 12 asthe other input. The first AND gate 260 receives the DOUT signal fromthe first two test cells 12. The output of each AND gate 260 isconnected to one A select part of the next test cell 12. In thisarrangement, the least significant test cell 12 in TCR 236 is set toToggle Mode (AB=01) and leading test cells 12 are set to operate eitherin Toggle Mode or Idle Mode (AB=11), depending on the logic level outputfrom the Count Enable Logic to the A inputs of each test cell 12. A testcell 12 will toggle when a PSA/PRPG test clock is applied if alltrailing test cells are set to a high logic level. A test cell 12 willremain in its present state (Idle) when a PSA/PRPG test clock is appliedif any trailing test cell is set to a low logic level.

[0265] Other functions previously described in connection with the testcell 12 may be performed by the testing device. The testing device maybe made to perform a toggle operation wherein data installed in theoutput TCR 236 during a prior scan operation can be made to togglebetween the true output pattern and its compliment output pattern duringeach PSA/PRPG test clock cycle. The toggle capability is useful duringthe testing of the device's output buffers and at the board level as asimple test pattern generator. The clocking for the toggle operation isidentical to that described in the PSA instruction.

[0266] The boundary scan path can also be read to determine the contentsthereof. The testing device remains in a normal operating mode duringthis operation. This instruction differs from the boundary scan andboundary data sample instructions in that the capture operation is notperformed. The boundary read instruction may be used to extract theresults of a PSA operation.

[0267] Although the present invention has been described in detail, itshould be understood that various changes, substitutions and alterationscan be made herein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A boundary scan test cell for use in conjunctionwith an integrated circuit containing application logic circuitrycomprising: a first memory for storing serial data and transmitting saidserial data to other test cells; and a second memory connected to saidfirst memory for storing output data.
 2. The test cell of claim 1 andfurther comprising circuitry connecting said second memory to theapplication logic.
 3. The test cell of claim 1 and further comprisingcircuitry to connect the output of said second memory to the input ofthe first memory.
 4. The test cell of claim 1 and further comprisinghold circuitry to maintain the output of said second memory at a givenstate.
 5. The test cell of claim 1 and further comprising togglecircuitry to alternate the output of said second memory between firstand second logic levels.
 6. The test cell of claim 1 wherein the outputof said first memory is connected to the input of said second memorysuch that said second memory can be loaded with a predetermined logicvalue.
 7. The test cell of claim 1 and further comprising circuitry toconnect said first memory to an input of the integrated circuit.
 8. Thetest cell of claim 1 and further comprising circuitry to connect saidsecond memory to an output of the integrated circuit.
 9. A boundary scantest cell comprising: a first memory; a first multiplexer for connectingone of a plurality of inputs to said first memory responsive to a firstcontrol signal; a second memory connected to the output of said firstmemory; and a second multiplexer for selecting an output from one of aset of inputs to the second multiplexer including the output of saidsecond memory responsive to a second control signal.
 10. The test cellof claim 9 wherein said first memory comprises a D-type flip-flop. 11.The test cell of claim 10 and further comprising clock circuitry forproducing a clock signal connected to said D-type flip-flop, such thatthe output of said first multiplexer is stored in said first memory ateach clock pulse.
 12. The test cell of claim 9 wherein said secondmemory comprises a D-type latch.
 13. The test cell of claim 12 andfurther comprising control circuitry connected to said latch forproducing a hold signal responsive to which said latch stores dataoutput from said first memory.
 14. The test cell of claim 9 wherein saidsecond memory includes inverted and non-inverted outputs, said invertedoutput connected as one of said inputs to said first multiplexer, suchthat a toggled output may be produced by the test cell.
 15. The testcell of claim 9 wherein the output of said first memory is connected asone of said inputs to first multiplexer.
 16. An integrated circuithaving boundary scan testing, comprising: application logic circuitryhaving one or more inputs and one or more outputs; one or more datainputs for receiving data into the integrated circuit; one or more dataoutputs for outputing data from the integrated circuit; a test datainput for receiving test data into the integrated circuit; one or moreinput test cells connected between respective data inputs and saidapplication logic circuitry, said input test cells comprising: a firstmemory for storing serial data; and a second memory connected to saidfirst memory for storing output data;
 17. The integrated circuit ofclaim 16 and further comprising: one or more output test cells connectedbetween said application logic and respective data outputs, said outputtest cells comprising: a third memory for storing information; a fourthmemory for storing information output from said third memory; a thirdmultiplexer selectively connecting one of a plurality of inputs theretoto said third memory, one of said plurality of inputs being connected tosaid test data input; and a fourth multiplexer for selectivelyconnecting one of a plurality inputs thereto to said respective dataoutput, the respective output from said application logic and the outputof said fourth memory being input to said second multiplexer.
 18. Theintegrated circuit of claim 16 and further comprising one or more outputtest cells connected between respective data outputs and saidapplication logic circuit, said output test cells comprising: a firstmemory for storing serial data; and a second memory for storing outputdata.
 19. The integrated circuit of claim 16 wherein said integratedcircuit includes a plurality of input test cells and further comprisingcircuitry for serially connecting ones of said first memories of inputcells.
 20. The integrated circuit of claim 17 wherein said integratedcircuit includes a plurality of output test cells and further comprisingcircuitry for serially connecting ones of said first memories of saidoutput test cells.
 21. The integrated circuit of claim 17 and furthercomprising circuitry for connecting the output of said first memory ofone of said input test cells to the input of said first memory of one ofsaid output cells.
 22. The integrated circuit of claim 16 and furthercomprising circuitry for producing a binary counting function at theoutput of said second memories of ones of said input test cells.
 23. Theintegrated circuit of claim 17 and further comprising circuitry forproducing a binary counting function at the output of said secondmemories of ones of said output test cells.
 24. A bidirectional testcell for use in an integrated circuit having an input/output pin fortransferring data to and from application logic circuitry, comprising: amemory for storing data; and circuitry to selectively connect theinput/output pin to the input of output of said memory responsive to acontrol signal indicating the desired input or output function.
 25. Thebidirectional test cell of claim 24 and further comprising circuitryconnecting the output of said memory to the application logic inresponse to said control signal indicating an input function.
 26. Thebidirectional test cell of claim 24 and further comprising circuitryconnecting the input of said memory to the application logic in responseto said control signal indicating an output function.
 27. Thebidirectional test cell of claim 24 wherein said memory comprises afirst memory, and further comprises a second memory connected to saidfirst memory.
 28. The bidirectional test cell of claim 24 wherein saidcircuitry to selectively connect comprises a tristate device connectedbetween the output of said memory and said input/output pin.
 29. Thebidirectional test cell of claim 28 and further comprising a firstmultiplexer having an output connected to said buffer for selectingbetween said output of said memory and an input to said test cell. 30.The bidirectional test cell of claim 29 and further comprising a secondmultiplexer having an output connectable to said memory for selectingbetween said input to said test cell and an input from said input/outputpin.
 31. A method of observing and controlling information input to anoutput from an integrated circuit containing application logic circuitrycomprising the steps of: providing a plurality of test cells havingfirst and second memories, one or more of said test cells connectedbetween the input to the integrated circuit and the application logicand one or more of said test cells connected between the output of saidintegrated circuit and said application logic; storing serial data insaid first memory; transmitting serial data between the first memoriesof the test cells; and storing output data in said second memory. 32.The method of claim 31 and further comprising the step of transferringdata from said first memories of the respective cells to the secondmemories of said respective cells.
 33. The method of claim 31 andfurther comprising the step of transferring data stored in said secondmemories to the respective test cells to the first memories of saidrespective test cells.
 34. The method of claim 31 and further comprisingthe step of maintaining the output of said second memory at a givenstate responsive to a control signal.
 35. The method of claim 31 andfurther comprising the step of toggling the output of said second memorybetween first and second logic levels.
 36. The method of claim 31 andfurther comprising the step of loading said second memories of the testcells with predetermined logic values.
 37. A method of observing datainput to a test cell and controlling data output from the test cellcomprising the steps of: selectively connecting one of a plurality ofinputs to a first memory responsive to a first control signal;transferring data from said first memory to said second memory; andselectively outputting the data stored in said second memory.
 38. Amethod of testing a logic section on an integrated circuit comprisingthe steps of: observing inputs to the logic section; and simultaneouslycontrolling the output to the logic section.
 39. The method of claim 38wherein said step of observing inputs comprises the step of selectivelystoring one of a plurality of inputs in a first memory.
 40. The methodof claim 39 wherein said step of simultaneously controlling the outputcomprises the step of selectively outputting an input to the logicsection of the output of a second memory.
 41. The method of claim 40 andfurther comprising the step of transferring data from said first memoryto said second memory.
 42. The method of claim 38 wherein said step ofsimultaneously controlling the output comprises the step of outputting astream of alternating logic values to the logic section.
 43. The methodof claim 38 wherein said step of simultaneously controlling the outputcomprises outputting a predetermined value to the logic section.
 44. Themethod of claim 38 wherein said step of simultaneously controlling theoutput comprises the step of outputting a counting sequence to the logicsection.